Analysis and Acceleration for Target Recognition

This thesis examined the hardware acceleration properties of automatic target recognition algorithms. It specifically focused on an algorithm produced by the SystemOriented High Range Resolution Automatic Recognition Program at the WrightPatterson Air Force Base. Analysis of this algorithm determined which calculations would be most suitable for and derive the most benefit from hardware acceleration. The algorithm was appropriately modified and restructured to ease its hardware translation while not significantly affecting the algorithm performance. A portion of the algorithm was then implemented and executed on a custom hardware board containing multiple field-programmable gate arrays, and the timing and algorithmic performance were compared with the corresponding software execution statistics. The near order of magnitude speedup showed the viability of custom hardware acceleration for target recognition algorithms. VI-A Company Thesis Supervisor: Paul D. Fiore Title: Senior Principal Engineer, BAE SYSTEMS MIT Thesis Supervisor: Dan E. Dudgeon Title: Senior Staff, MIT Lincoln Laboratory